Today’s complex systems often feature a multitude of devices incorporating several different logic power families. In order for these mixed-mode systems to operate properly, some type of voltage translation and voltage clamping is needed. This allows the different I/O signals to communicate with each other without damage from overvoltage effects.
A simple and inexpensive way to accomplish this translation is through the use of an FET voltage-clamp circuit (Fig. 1). By connecting one of the I/O signals to the gate of the FET, the other side becomes the VREF voltage input. As a result, the designer can regulate the outgoing voltage level by adjusting VREF, which should not exceed VDD (0.8 V for proper operation). The output high level will be approximately 0.7 V, a diode-drop lower than VREF.
In this example, we can adjust the output high level (VOH) from 0.1 to 3.5 V. Therefore, any potentially damaging voltage levels are prevented from reaching the next stage of I/Os. Either port can be used as the low-voltage side. In addition, the device is bidirectional. Because it’s a FET switch, data can be translated at speeds of 100 MHz or greater without severe signal degradation.
The FET can be used as a voltage-limiting device in several circuit arrangements. In the first example, a pull-up resistor is used (Fig. 2). With this arrangement, the output can swing between 0 V and VDPU. The second configuration relies on a pull-down resistor (Fig. 3). This enables the output voltage to fluctuate between 0 V and VREF.
By using an open-drain device to drive the FET, the input to the device can be controlled (Fig. 4). The open-drain/collector will be low when the input signal is high and the FET will pull the signal high when the input is low. Consequently, a 0-V to VREF inverted signal is produced on the input, while a 0-V to VDPU signal results on the output of the FET clamp. This kind of circuit is commonly used on the open-drain CPU-type interfaces found in personal computers. Such a configuration can isolate and eliminate any damaging spikes or glitches from the driving signals.
am a student of physics and electronics.i need an inverter simple design tips using fets as the power transistors.especially with PWM ICS(SG3524)and others.thanks
adelaja -May 14, 2008
I am a Electrinics &communication Engineering student.I don't know the JFET &about details so you send the CG in JFET>
vinothkumar -August 29, 2005
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