[Product Innovation]
Programmable SoC Delivers A New Level Of System Flexibility
Implementing reconfigurable analog and digital building blocks, a new chip dynamically adapts to system needs.
System-on-a-chip (SoC) solutions have primarily been digitally intensive, comprised of a microcontroller/DSP core, memory, logic, interfaces, and other similar functions on the same die. In terms of flexibility and reconfigurability, these CPU-centric designs have been dictated by the programmability of the on-chip processor and memory. Until now, analog functions have been minimally programmable. Plus, the peripherals and I/Os surrounding the processor have been fixed for given system requirements.
But as the system needs change with evolving standards, the SoC landscape comes under constant pressure to rapidly adapt to these standards. Cost and time-to-market issues are demanding a new level of system flexibility and reconfigurability. Therefore, users are seeking a device architecture that can be quickly molded to fit system architecture and software needs at the same time as peripheral and I/O configuration can be dynamically redefined at run time.
This has motivated startup Cypress MicroSystems Inc. to exploit its parent's strengths in programmable technologies, intellectual properties (IPs), and microcontroller architectures. By combining these attributes with process capabilities, the company has spawned a new generation of high-speed programmable SoC devices, called PSoCs. Cypress MicroSystems, a creation of Cypress Semiconductor Corp., was launched in September 1999 to accelerate the development of PSoC solutions for the fast-growing communications, control, and data-acquisition markets.
In short, the PSoC shifts the processor-centric SoC toward the reconfigurability of the I/Os and peripherals on-the-fly. "It enables a designer to extract more value out of the same resources on-chip," states Nathan John, director of marketing at Cypress MicroSystems.
According to Dennis Seguine, principal applications engineer at the company, this is aided by a PC-based integrated design environment that's tightly coupled to the PSoC architecture. "Using this high-level development software, a user can quickly configure and reconfigure analog and digital arrays of the device on a PC screen. And upon satisfaction, the user can then map the system configured onto the PSoC chip by the click of an icon," Seguine remarks.
By allowing the user to work with menus and graphical icons on-screen, this Windows-based IDE permits a user to drag and drop higher-level functions in appropriate boxes and create the end system in minutes. Once the system configuration is finalized, it's stored in the flash memory on-chip. Upon power-up, the contents of the flash are transferred into register space that holds the configuration information. Also, this system configuration can be easily and quickly modified as the system requires change.
Built around a high-performance microcontroller core, a PSoC is created by adding a collection of analog and digital building blocks that allow efficient implementation of peripherals and I/Os used in a variety of embedded applications (Fig. 1). These building blocks, called SoCblocs, enable the designer to define unique functions during the configuration of the device.
In fact, these SoCblocs are further interconnected into what are called user modules. "The user module is a useful function analogous to an on-chip peripheral," John says. "Furthermore, SoCblocs can be interconnected in two fundamental ways. In parallel, they extend the precision of a function. For example, a wider timer or a higher-precision analog-to-digital converter (ADC) can be achieved. In serial, the building blocks can be configured to accomplish processing that would otherwise require multiple off-processor chips. For instance, an output of a sensor can go through a prescale amplifier, bandpass filter, and an ADC on the same PSoC chip."
The first member of the PSoC family to be implemented holds 12 analog and eight digital SoCblocs. The 12 analog SoCblocs consist of four continuous time (CT) building blocks, and eight switched-capacitor (SC) blocks (Fig. 2).
While the CT functions are optimized for building programmable-gain amplifiers (PGAs) with multiplexed inputs and outputs, differential amplifiers, and very fast comparators, the SC circuits can be interconnected to achieve functions like programmable filters, successive-approximation-register (SAR) ADCs, multislope ADCs, digital-to-analog converters (DACs), and other similar functions. Potential circuits that can be generated by the digital arrays are such functions as timers, counters, UARTs, CRC generators, pulse-width modulators (PWMs), and various other digital functions.
Using on-chip analog and digital multiplexers and switches, these SoCblocs are interconnected to achieve higher-level functions, labeled user modules by designers at Cypress. To make life easier for the user, the low-level details of the SoCblocs and their interconnection techniques are transparent to the user. The company has taken the trouble of interconnecting the underlying analog and digital SoCblocs and creating a library of analog and digital user modules.
Cypress has crafted about 40 analog user modules. Some of these are SAR ADCs, incremental ADCs, delta-sigma ADCs, and DACs. Also, there are differential comparators, programmable low/high/bandpass/bandstop filters, PGAs, sample-and-hold amplifiers, waveform generators and detectors, and modulators and demodulators. Likewise, the digital portion offers nearly 30 user modules, which include timers, counters, PWMs, serial transmitters/receivers, full UARTs, SPI master/slave interfaces, CRC generators, pseudorandom generators, and motor-control circuits.
Both the analog and digital user modules can be combined to configure the system for a specific application. To demonstrate this capability, consider a four-channel pressure data-acquisition system. In this design, differential outputs from four pressure sensors are fed into two on-chip 4-by-1 multiplexers. Then, the multiplexer outputs are fed to a high-impedance instrumentation amplifier (IA) that's made of two analog CT SoCblocs (Fig. 3). This amplifier can be configured to have the same fixed gain for all of the channels or a separate programmed gain for each channel, depending on calibration requirements. Additionally, the IA drives a two-pole, biquad low-pass filter that's constructed from two analog SC SoCblocs.
the site is useful enough,for starters like me. but i need to know about designing filters in PSoC.how and where can i get help from?
suma -April 27, 2005 (Article Rating: )
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