Shorter time-to-market cycles and the increasing densities of both programmable logic devices (PLDs) and system-on-a-chip (SoC) ICs have made design simulation an essential part of the development cycle. The growing practice of designing hardware at a higher level of abstraction than register-transfer level (RTL) means that simulation is becoming a part of the design process. Effective simulation improves design reliability while reducing the development cycle. Yet even with modern software tools, producing simulations for complex designs can be difficult and error-prone.
The benefits of simulation on any single project are readily apparent. Simulation enables design engineers to test for wide ranges of conditions that may be difficult to generate using prototypes. When design changes are easier and less expensive to make, designers can shorten cycles and improve quality by verifying functionality earlier in the design cycle. Plus, simulation and modeling tools provide an environment where designers are better able to observe and analyze their design's behavior.
This is so important that some logic vendors see differentiation in developing and providing their own simulation tools. Others opt to license tools from specialty vendors, such as Model Technology, and offer several different levels of simulation, depending on the needs of the design team.
But, simulation modules developed for smaller projects aren't easily scalable to larger and highly complex designs, which makes it difficult to build an effective test bench. There also is little guidance on how detailed the simulation model should be to capture the level of implementation necessary to provide adequate information (see "Modeling Of Embedded Processors In PLDs," p. 96).
Virtually all EDA tool chains include facilities for simulation. PLD vendors, like Altera Corp. and Xilinx Inc., give away entry-level versions of simulators with their devices. In fact, that may be part of the problem with simulation. These versions enable new HDL designers to experiment by creating small HDL designs and simulation test benches.
Critical to effectively using HDL simulation is the ability to build test benches that are both scalable and reusable as designs grow more complex. Engineers who develop a methodology emphasizing these goals will find that simulation pays off in better designs and less rework. Plus, new software tools are enabling engineers to implement simulation in new and powerful ways to better debug and verify more complex designs.
Using Simulation In Design
Simulating a design is a standard practice for ASIC designers and others working with high-density devices. Verilog and VHDL simulators replaced older simulators, which generally had separate languages for netlist, models, and test bench uses (Fig. 1).
Simulation can occur at three points in the design process: at the RTL, during functional design and simulation, and at the gate level. Once the design is created, it must be verified prior to the RTL to ensure that its functionality is as intended. At this point, the test bench should be created or expanded, so that it covers the range of tests needed to exercise the design. It will be used throughout the FPGA flow to verify the functionality of the design at the register-transfer, functional, and timing-gate levels.
A test bench, a separate set of VHDL or Verilog code connected to the design's inputs and outputs, is an integral component of simulation. Because these stay constant through synthesis and place-and-route routines, the test bench can be used at each stage to verify functionality. Because of the complexity of large designs, there are significant challenges in building testing models and test benches.
Two ways exist to implement a test bench. One method is to gradually create your own test bench over a period of time, adding the necessary components for testing features of specific designs. Here, it's critical to design both components and tests that are modular and reusable across different designs, and even across different design teams.
This approach requires careful planning and close coordination between the various design teams, as well as the use of a central repository for tests. You're not likely to see the full benefits of this home-grown approach in the first couple of projects. But performed properly, it could become one of your most valuable design tools.
The other way to implement a test bench is to buy a commercial model library, such as the FlexModel library from Synopsys Inc. This type of model won't implement your specific designs, so you will still have work to do on your test benches. But commonly, they will model the off-the-shelf components and IP that you're using. Additionally, they have the advantage of already being optimized and verified. Because these libraries vary in their offerings, you will have to search for suitable components. FlexModel, for example, includes a wide range of microprocessors, controllers, and bus interfaces. Commercial libraries jump-start the simulation test bench, but are by no means a complete answer.
Test bench automation tools enable engineers to more easily specify and create the test bench environment. These tools provide built-in test generation, reactive response checking, and functional coverage analysis. They should include a high-level verification language, too, that will increase engineering productivity and verification quality by eliminating much of the laborious process of creating high-coverage test benches.
Performance is a key aspect of simulation, especially as your designs grow larger and more complex. If the design encompasses hundreds of thousands or millions of gates, simulating all aspects of the design, and running the simulation test cases many times can take up an inordinate amount of debugging and verification time.
One way to improve simulation performance is by speeding up the simulator through the use of more efficient code. This lies in the realm of the simulator vendor. But it's incumbent on the design team to seek out the most efficient simulator for serving its purposes.
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