A Unique Discrete Zero-Crossing Detector

A zero-crossing detector delivers an output pulse that synchronizes other circuitry to the transitions through zero volts of a sinusodial source for both polarity excursions. This detector, which was developed to operate from the ac power line, includes a unique negative-voltage detector/level shifter.

In Figure 1, Q2/Q3 appear to be operating in their common-base/common-collector modes, respectively. However, in this application they actually function in the common-emitter mode! Essentially, the output resulting from their combined interactions is that of an npn transistor turned on by a negative current source.

The major goals for this design were: 1) efficiency—minimum power consumed while operating, and 2) the circuit should allow no dc current to flow during power outages. The high impedance presented to the power line by the divider/filter (formed by R1, C1, R2, and R3) keeps power loss very low and effectively suppresses noise spikes from reaching the semiconductors. As required, all transistors will be off during the absence of line voltage. For the values given, the detector outputs a pulse 200 ms wide and the network attenuates spikes up to 15 ms wide by more than 27 dB.

For this detector to function properly, the transistors used must possess reasonably high betas (β > 75) due to the low drive currents allowed by the divider. It’s also desirable, but not necessary, that they be complementary matched pairs, both in beta values and saturation levels. Matched conditions are assumed in the circuit discussion that follows.

Q1 is turned on and kept on while the power line is positive and operates in standard npn fashion. When zero volts occurs on the line, the Sync output goes high. As the line goes negative, Q2 turns on and Q2/Q3 perform their magic. As shown in Figure 2, Q2’s emitter will be clamped at −V_BE, and the majority of the negative emitter drive current received will flow into Q3’s base. This current then is amplified by Q3 so that:

I_E3 = (β + 1)I_B3 = (β + 1)(β/β + 1)I_E2

Therefore, I_E3 = βI_E2

while Q2/Q3 are in a linear mode pulling Sync low. What are the operating voltages when saturation is reached? With −V_BE at Q2’s emitter, (+V_SAT − V_BE) at Q2’s collector/Q3’s base, Q3’s emitter is +V_BE, up from its base and therefore equal to + V_SAT. The performance exhibited again appears to be that of an npn. Remember, though, that a negative drive current is turning it on.

When Sync is high, charge is stored on the junction and stray capacitances at Q3’s base. If V_CC is greater than Q3’s base-emitter breakdown voltage, then some bleeder path must be provided to remove this trapped charge. Otherwise, breakdown of that diode will occur when Q1 pulls Sync low. Not an ideal situation! R5 accomplishes this task and can be relatively large due to the small value of capacitance involved.