When designing battery-operated devices, battery contact chatter can be prove to be a difficult problem to overcome. When the chatter occurs at a critical time, the results can often be devastating. For instance, if a memory write takes place during a power interruption, memory corruption can occur, and checksums may be incorrectly computed or not be written at all.
A great tool in the arsenal of battery-powered device designers has been the low-dropout (LDO) regulator. These regulators use PNP devices for their output devices. As a result, they have dropout voltages that equal the VCESAT of the PNP rather than a couple of VBE drops. For example, the LP2951 has a dropout voltage (at IOUT = 100 mA) of 600 mV while the dropout voltage of the LM317L is almost 2 V under the same conditions. This feature of LDO regulators allows designers to gain an additional volt or more of precious end-of-life battery potential.
Several manufacturers of regulators provide output signals that indicate a power error condition. These circuits generally monitor the output voltage of the IC and activate a signal if the output voltage falls out of bounds (Fig. 1). This is an after-the-fact error detection. By the time that the microprocessor sees the warning, the output is already out of specification. In the ubiquitous LP2951, the error pin goes low only after the output is already 7.5% below its nominal output voltage. Many logic devices call for regulation within ±5% of nominal. The problem with this type of error sensing is obvious.
The circuit configuration shown senses any interruptions in the regulator input current instead of the output voltage (Fig. 2). This is a more proactive error-detection scheme than sensing output voltage. The input current interruption can be sensed while the output voltage is still within regulation limits, saving valuable milliseconds of operating time. The time gained can be used to do those emergency “clean up” tasks that are required for a safe shutdown while the regulator’s output voltage is still within specification.
To accomplish this current sensing, a second PNP transistor (Q2) has been added (in a current-mirror configuration) to the pass PNP of the classical LDO topology. The transistor would be scaled so that Q2 conducts a fraction of the current that flows through Q1 to limit power consumption. It also is possible that R2 could be sized so that the transistor is normally in saturation (minimizing the power dissipation of this transistor and load). The voltage across this load resistor is compared to a known voltage (VREF2). If this sense voltage is lower than VREF2, then the —ERROR pin goes low, signifying an error event.
What distinguishes this approach from the standard ERROR signal of other LDO regulators is that the output hasn’t begun to fall at the point the error signal is generated. If one knows how long it takes to finish the longest critical event that the microprocessor performs, it’s easy to size the post regulator filter capacitor to keep the voltage drop over this time to an acceptable level. The battery powered device then can do whatever is required to put the instrument to “sleep” while minimizing the potential for serious instrument malfunctions. This could include the computation and writing of a checksum to EEPROM memory.
In practice, designers would probably want to retain the output-voltage sensing of the conventional LDO circuit. Otherwise the voltage could drop out of regulation with no error detection. Optimally the outputs of the two error-detection circuits (current sensing and output-voltage sensing) could be combined. The LP2951 output is an open collector output. If the proposed current-sensing circuitry was added to this IC, the collectors of the two comparators could be connected. Other enhancements could include a pulse-stretching circuit or a latch on the error output.
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