Digital-to-analog converters (DACs) don't always garner the attention of their analog-to-digital converter (ADC) counterparts because DAC performance isn't a limiting factor in many applications. Nevertheless, monolithic DACs still play an important role in system design. In many applications, a large number of signals require digital-to-analog conversion. DAC vendors can reduce the board space required for data conversion by increasing the number of digital-to-analog channels that they can pack on a chip or by raising the conversion rate to achieve the same effect.
The vendors can also address power budget issues by limiting the power consumed by each DAC while still satisfying critical noise performance goals. One vendor recently introduced a family of 8- to 12-bit DACs that limit current consumption to just a few microamps per channel by operating off a low 1.8-V supply. Given the demands for lower power consumption in portable, battery-powered applications, it's likely that other vendors will soon follow suit. The new DACs combined with the existing 1.8-V ADCs may help some systems to operate directly off the battery without a boost circuit.
For systems that require a single channel of digital-to-analog conversion, DAC developers can help by migrating their devices to smaller packages and by bringing related functions like voltage references on-chip. For some applications, the higher precision of an external voltage reference will be required. The current state-of-the-art now gurantees a few parts per million of precision in SOICs as small as 3 by 5 mm. Going forward, IC vendors will be challenged to achieve the same or better accuracy in even smaller surface-mount packages.
Recently, some data-converter companies have begun applying system-in-a-package (SiP) techniques to increase device functionality, ease-of-use, and performance. The SiP approach copackages two or more die, sometimes stacking them. Not only does this approach produce very compact designs, it also greatly reduces the parasitics in the chip-to-chip interconnects, enabling high-speed operation.
Copackaging aside, parasitics are now becoming a concern in the development of some single-chip DACs. As converter speeds approach the gigasample-per-second range, the parasitics associated with the leadframes and bond wires in traditional IC packages begin to limit DAC performance. Fortunately, the use of flip-chip assembly and BGA-style packages can greatly reduce package parasitics and allow the DAC to perform up to the limitations of the silicon.
TOP TEN
PRECISION DACs are slipping into smaller packages. For example, in the next six months, Analog Devices plans to offer 8- to 14-bit DACs in the SC-70.
THE MIGRATION TO FINER semiconductor process geometries is creating faster data rates for high-speed converters. But in some cases, chip packaging is hampering the move to higher speeds. In leadframe packages with bond wires, the parasitics associated with these interconnects are starting to limit the speed that data can be moved in and out of the silicon. Bumped dies, which remove bond wires and reduce package footprint, will enable data converters to move to higher speeds. Consider an Analog Devices' 16-bit DAC that achieves 600 Msamples/s in a bond-wire package. According to the company, it will be necessary to adopt a bumped die package to increase the DAC's performance beyond 1 Gsample/s. The new package will remove parasitics and allow the inclusion of decoupling capacitors in the package.
THE SYSTEM-IN-A-PACKAGE concept will start to make inroads in the data converter area. Until recently, multichip packages, whether employing stacked die or side-by-side die, were considered too exotic for data converter ICs. Now these packaging techniques are viewed as another option for increasing converter performance and functionality.
THE MIGRATION TO LOWER SUPPLY VOLTAGES will push power consumption to new lows, benefiting portable applications such as blood glucose monitors. Recently, Maxim Integrated Products introduced 8-, 10-, and 12-bit DACs that operate from a 1.8-V supply. (Part numbers are MAX5510-MAX5515/MAX5520-MAX5525/MAX5530-MAX5535). These single and dual converters limit current consumption to just 4 µA/channel. That low value is obtained with a precision voltage reference on-chip. For applications that run off two 1.5-V cells, where each cell discharges to 0.9 V, the 1.8-V supply allows the DACs to operate directly from the battery.
HIGH-RESOLUTION DACs are achieving higher density to provide the large number of digital-to-analog channels required by automatic test equipment (ATE). There are 14-bit DACs with as many as 32 channels, and 16-bit versions with similar density will soon arrive.
BETTER VOLTAGE REFERENCES will enhance the DAC's accuracy in-system. External references are being honed for increased precision, smaller size, lower power consumption, and lower noise. Of course, some of these goals conflict with one another. For example, as package size shrinks, package stresses make it more difficult to obtain the desired accuracy. Another factor is that shrinking the die limits the amount of silicon available for voltage-correction circuitry. Similarly, low noise and low power consumption typically must be traded off. Nevertheless, it's now possible to get precision voltage references guaranteed at 3 ppm in SOIC packages as small as 3 by 5 mm. In the even-smaller SOT-23, 7-ppm references are available. Look for vendors to try and improve these levels of performance in the coming year.
GENERAL-PURPOSE DACs are chasing greater accuracy and higher density. Among 12-bit string-architecture DACs, the low-cost, low-power devices now exhibit 1 LSB of differential nonlinearity (DNL) and 4 to 8 LSB of integral nonlinearity (INL). In the coming year, those same devices should be available with an improved INL of 1 LSB.
GENERAL-PURPOSE DACs AT THE 16-bit level will seek reductions in linearity error. Low-cost models now offer a linearity error of 0.19%, which corresponds to 8-bit linearity. In 2004, vendors will offer 0.024% (12-bit) linearity for these chips with pricing at $5/part or less.
FURTHER IMPROVEMENTS IN GENERAL-PURPOSE DAC linearity will require moving away from laser trimming of thin-film resistors to achieve good linearity. In the next two years, companies like Texas Instruments will hope to exploit less expensive alternatives to laser trimming. New chips will exploit improvements in process technology in combination with the use of one-time programmable cells at final test. In addition, DAC designers will employ different topologies that allow for calibration techniques.
A SURPRISING LONG-TERM DEVELOPMENT may be the adoption of LVDS interfaces among general-purpose DACs. In terms of performance needs, SPI and I2C interfaces have more than enough speed for these DACs. However, as LVDS grows in popularity, general-purpose DACs will increasingly be found next to components with this high-speed serial interface. Having the LVDS interface on the DAC would merely simplify system design for users.
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