Not many years ago, the only packaging issue that routinely concerned
most chip designers was pin count. Package problems belonged to manufacturing,
and designers were happy to "toss the project over the wall" once the
prototypes had been tested successfully. Today, though, packaging is no
longer an afterthought in chip design.
In the last few years, performance demands have changed rapidly, bringing
lower voltages, increases in current, higher frequencies, and faster rise
times to high-end digital and mixed-signal ICs (Fig. 1).
Just as these factors modify the operation of the chip circuitry, they
also alter the electrical requirements of the package. Designers who ignore
these side effects in the package risk product failure.
In addition, rising package costs reflect the growing difficulty of
keeping the package environment from interfering with chip operation.
Multiple power and ground planes, and special routing and vias combine
to raise the cost of the package as high as, or even higher, than the
silicon it contains. Used appropriately, these features enhance the operation
of the device, but they also serve to complicate the overall design picture.
Fortunately, package modeling tools have come a long way in recent years,
providing designers with ways to evaluate the behavior of a chip within
its package. Electrical models complement thermal and stress models to
provide a complete picture of how the package will behave in operation.
Together with models of the silicon circuitry, electrical package models
can be fed into simulation tools such as Spice. Based on the results of
simulation, a designer can change the chip layout or packaging features
to ensure that the design works properly. Before going to the appropriate
packaging house or vendor, however, a number of steps can be taken to
facilitate the vendor-designer interface, to ensure a successful design.
The Package Environment
Although package modeling tools perform complex calculations, they cannot
yet make critical design decisions. Therefore, the chip designer must
understand how package characteristics can adversely affect a design.
The designer can then tailor the chip for the package and make appropriate
trade-offs to correct package problems that show up in simulation.
In a general way, a package behaves as a low-pass filter, because the
RLC structure attenuates the voltage for fast changes in current (Fig.
2
). So, at the very least, modeling tools must be able to predict
the effects of resistance, inductance, and capacitance in the leads during
worst-case chip operation. It is important to keep in mind that conductors
within a package are not resistors, capacitors, and inductors in the sense
of point features, but instead have distributed RLC properties along the
length of the leads. Additional factors that may need modeling, depending
on requirements, include lead impedance, signal timing, and the effects
of energy dissipation throughout the package at high frequencies.
One of the axioms of package modeling is that a parametric value for
a single lead indicates very little by itself. Any meaningful analysis
must include coupling to all significant current paths, as well as any
nearby signals that are potential sources of interference. Moreover, the
model must be used in conjunction with simulation tools to provide a realistic
picture of the package environment.
Package modeling considerations hold true for both mixed-signal and
digital designs. Mixed-signal applications tend to use simpler packages
with lower pin counts. They operate efficiently at high frequencies due
to very short, low-inductance leads, and an abundant distribution of ground
pins. Digital devices have generally required higher pin counts, increasing
the complexity of the package, and, in some cases, requiring multiple-layered
packages with ground (GND) and power (PWR) planes. As a result, each type
of design receives a different emphasis during package modeling, though
the overall concerns are the same.
In many designs, the overriding package problem is inductance, which
is responsible for much of the voltage drop across leads. A significantly
damaging effect of high inductance is ground bounce, in which the ground
voltage level rises during rapid changes of current levels as the device
operates. Power droop, in which the supply voltage (VSS) level
falls, can occur as well. In both cases, inaccurate reference voltages
can interfere with switching thresholds and cause bit errors, or restrict
the operational range of signals.
The inductance of a lead considered in isolation (LSELF)
depends largely on the section geometry and the length of the lead, though
the latter relation is not linear. LSELF values must be combined
with mutual inductance (LMUT) values among the signal paths
to obtain the effective inductance (LEFF) when predicting the
behavior of the package. LEFF reflects how the magnetic fields
within the package behave as signals propagate through the circuit. Factored
with the current change rate (di/dt), LEFF yields a voltage
drop. Faster circuits, therefore, yield more voltage stability problems
if LEFF remains the same.
Obviously, the challenge is to keep LEFF as low as possible,
because rise times are likely to become faster and current levels higher
in future designs. Physical isolation of conductors has a large effect
on LMUT values, and thus on LEFF. All other things
being equal, a pair of leads that are adjacent have higher LMUT
values than a pair that are isolated.
To predict inductance effects accurately, the modeling software not
only has to determine dynamic LEFF values for the leads, it
also has to analyze how PWR and GND planes affect inductance in different
areas. PWR and GND planes may serve to minimize overall LEFF
in the package, especially in areas where they couple the current return
paths to the signal lines. The software must be able to evaluate how local
LEFF values are modified by the routing of signals, the placement
of exit points for current sources and sinks, and irregularities such
as holes in the plane for special structures.
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