The world of IC and system design sees process technologies and system architectures come and go at mach speed. The tools designers require to keep pace change just as quickly. For those who simply must stay abreast or else, the 41st Design Automation Conference (San Diego, June 7-11) is the place to get on top of the trends in tools, methodologies, and technologies. More than 10,000 attendees are expected to peruse the offerings of over 170 exhibitors.
This year's technical program includes seven tracks: business; system-level design and verification; power; logic design and test; embedded systems; nanometer analysis and simulation; and physical circuit design. Attendees will be able to choose from over 200 panels, papers, sessions, workshops, and tutorials.
But for users of EDA software and associated hardware, there always are multiple reasons to make the annual pilgrimage to DAC. The technical sessions go hand in hand with the activities on the show floor and in the maze of fortress-like demonstration suites. The sessions get you up to speed on the latest technologies and methodologies. But there's nothing like seeing them in action, bringing the theoretical into practical reality.
DAC is often a show where one can watch industry trends coalesce. One nascent trend over the past few years is the move to a level of abstraction higher than register-transfer level (RTL). In San Diego, a number of established EDA vendors and startups will display the latest in electronic-system-level (ESL) tools and methodologies.
Summit Design is among the more established ESL houses. Version 4.0 of its flagship Visual Elite tool now offers built-in SystemC native constructs that accelerate modeling and verification, making it intuitive for hardware designers as well as for C/C++ coders. The tool offers visibility into SystemC code from both hardware and software perspectives (Fig. 1). A Design introspection view is hardware-centric, while a Code introspection view offers a C/C++ look at the language structure. Transaction-level verification tools also were added. Prices start from $15,000.
Another ESL stalwart, CoWare, will show the latest release of its ConvergenSC ESL design platform, which combines new hardware/software partitioning capabilities with platform-assembly features. Also in the CoWare stable is the LISATek tool. It enables embedded processor designers to automatically model their work at a high level of abstraction, as well as generate instruction-set simulators and a complete set of associated software tools (including a custom C compiler).
Debug continues to evolve, spreading in its influence to cover all phases of the design cycle. Novas Software will divulge an expanded strategy/roadmap to address advanced debug and system-on-a-chip (SoC) development beyond the traditional definition of hardware debug. Novas is building upon its existing core debug foundation to provide a platform that spans the full design cycle.
Some new capabilities Novas will show include support for standard communications/bus protocols with additional transaction-level interfaces that target ESL requirements. The company will unveil a suite of design-analysis tools, including the production release of the Verdi post-simulation assertion checker along with new visualization enhancements. There also will be links from Novas' debug systems to physical layout tools.
Celoxica's DAC booth will feature the first public showing of the company's safety and security demonstrators built using BAE Systems' and Celoxica's technology and RC series development platforms. A prototype fingerprint-matching engine based on BAE Systems' LEARNN neural-network algorithm processing technology will be running on a Celoxica RC200 development board. The LEARNN technology is implemented in programmable logic using Celoxica's C-to-FPGA synthesis tools.
Implementing DSP functionality on FPGAs has become quite a popular trend. AccelChip's DSP Synthesis tool gives users of the MathWorks' Matlab algorithm-based design environment a direct path to silicon, automatically generating synthesizable RTL from Matlab algorithms (Fig. 2). Building on its earlier AccelFPGA tool, AccelChip's DSP Synthesis tool supports FPGAs, ASICs, and structured ASICs. It also works in enhanced flows with the MathWorks' Simulink and Xilinx's ISE and System Generator tools.
DSP Synthesis generates cycle-accurate models for Simulink and other DSP-based component integration environments. In so doing, it enables system-level verification of all components using libraries and math-based models. It also exports models that are verified against the golden Matlab source code into Simulink.
The long-awaited formal announcement of Forte Design Systems' Cynthesizer finally comes at this year's DAC. Cynthesizer is touted as the first behavioral synthesis tool to offer a direct implementation path from SystemC to RTL, verification, and cosimulation. It automatically generates optimized RTL from a C++/SystemC algorithmic design description.
Using untimed C models, Cynthesizer builds a fully timed RTL hardware implementation based on the designer's constraints. It outputs industry-standard RTL specifically targeted for a number of downstream flows and tools. Cynthesizer's behavioral synthesis functionality includes automation of tasks such as operation scheduling, cycle timing, control, and datapath design and resource allocation. Pricing is still being determined.
Arteris, a startup gearing up to deliver its network-on-chip (NoC) technology in the form of IP and high-level design tools, will have a low-profile presence at DAC. To address the challenges of on-chip interconnections and communications, the company plans to offer high-level-flow, EDA-style tools and capabilities for NoC architectural analysis and design exploration (i.e., system-level language capture, synthesis, and simulation). With such tools, designers can use languages like SystemC and SystemVerilog to model the network, drive the tools, and explore options for implementation.
FRONT-END DESIGN
These days, more designers are at least interested in beginning the design process at a level of abstraction higher than RTL. It's a good thing, because all designs must eventually pass through the RT level in their journey toward implementation. In the traditional "front end" of the process, much DAC activity surrounds new products and technologies.
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