211 results found for Product Innovation, displaying items 1 - 20
May 18, 2006
Signal Analyzer Boosted By WCDMA/HSDPA Option
Combined with the Signature signal analyzer, the MS2781A WCDMA/HSDPA Modulation Quality Measurements option provides a suite of measurement capabilities to developers of base stations and related subsystems.
—
Staff
December 23, 2002 Programmable Clock Generator Solves System-Timing Woes
TIMING WITHIN ALL DIGITAL AND MOST MIXED ANALOG/DIGITAL SYSTEMS COMES DOWN TO ONE DEVICE—THE CLOCK GENERATOR. But with mounting system complexity, a single clock oscillator delivering just one digital signal is no longer adequate. These days,...
—
Dave Bursky
October 28, 2002 BiCom-III Process Triples Speed, Halves Noise
Dubbed BiCOM-III, TI's recently announced silicon-germanium (SiGe) complementary bipolar-CMOS manufacturing process integrates both NPN- and PNP-type bi-polar transistors. The result of this first-ever integration is speeds up to three times faster...
—
Tets Maniwa
October 28, 2002 Superfast Op Amps Break 2-GHz Bandwidth Barrier
Until now, very high-speed Operational Amplifiers (OP AMPS) have offered a top bandwidth of about a gigahertz. The addition of silicon germanium (SiGe) to a high-speed bipolar-CMOS process results in a family of fixed-gain, voltage-feedback op amps...
—
Tets Maniwa
October 14, 2002 Multifunctional HyperTransport
HyperTransport (HT) is a high-speed, low-latency, point-to-point link. The current design handles peak rates of 102.4 Gbits/s. It has support from a wide range of suppliers and is incorporated into processor chips, such as Broadcom's BCM1125H,...
—
William Wong
October 14, 2002 Quad 64-Bit Multiprocessor Targets Comm Applications
Getting data to and from a processor quickly is key to high-performance network processing. Broadcom's new BCM1400 multiprocesssor tackles this problem with a trio of flexible advanced HyperTransport/SPI-4 Phase 2 links. Of course, packing four 64-bit...
—
William Wong
September 30, 2002 P1500: The Standard For Embedded Test
In current system-on-a-chip (SoC) development, no standard access mechanism exists for testing embedded logic cores. Each core provider develops its own process for isolating the core and testing it. These methods are sometimes in conflict, making it...
—
Dave Bursky
September 2, 2002 AC-DC Switcher IC Yanks The Plug On Linears
Over the past few decades, switching power supplies have become an increasingly popular alternative to linear power supplies. Also commonly called switchers, they offer higher efficiency, smaller size, and lighter weight than linears. These advantages...
—
David G. Morrison
August 19, 2002 60-A Quarter-Brick DC-DC Converter Keeps Its Cool
With the migration from Schottky Rectifiers to Synchronous Rectification a few years ago, dc-dc converters achieved dramatic improvements in efficiency. As an example, consider a 30-A telecom-style dc-dc converter designed for the popular 3.3-V supply...
—
David G. Morrison
August 5, 2002 Tool Makes Sure I/O Designs Measure Up To Spec
Standing as they do as the bridge between the digital and mixed-signal world of System-On-A-Chip (SOC) cores and the largely analog world of the circuit board, I/O cells are an increasingly difficult beast for designers to tame. Not only must I/Os...
—
David Maliniak
July 22, 2002 Comm Processor Offloads Host, Delivers Gigabit Data Streams
As data transfer rates increase and system integrators strive to bring more services and features to the communications systems they're crafting, current-generation communications processors are running out of steam. Future enterprise routers, media...
—
Dave Bursky
June 24, 2002 CMOS DC-DC Controller Tackles High Voltages
Pressure to speed designs to market without compromising reliability and performance isn't the only compelling reason to adopt more integrated voltage converters or controllers in power supplies. The ability to build smaller, lighter, and more...
—
Ashok Bindra
June 10, 2002 The ASIC Vendor's View Of RTL Rule Checking
Frequently, the customer netlists sent to ASIC vendors' design center engineers for physical implementation are riddled with problems. "If you have timing or congestion problems in implementations, it's likely that they started with the RTL and were...
—
David Maliniak
June 10, 2002 Rule Checker Takes RTL Analysis Into The Physical Realm
At one time, the relationship between logic designers and physical implementation specialists was simpler. Front-end designers had long been accustomed to providing their ASIC vendors with a timing-qualified, gate-level netlist that was blessed by...
—
David Maliniak
prev. page
[1]
