1094 results found for Web Exclusive, displaying items 1 - 20
July 21, 2008
Still Working On My Solar-Panel ROI
“The meter’s running backwards!” I wrote that line in August 2006, quoting my wife Vicky, who was entranced by the most visible manifestation of what our just completed rooftop grid-connected solar system was achieving (“A Solar Story,” ED Online 13242). While that column covered the technical details of its installation, this story is about the economic advantages we’ve seen since then.
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Don Tuite
July 17, 2008
The Power Of The Portfolio Can Maximize Software Development
Today, most companies target the needs of their prospective customers by creating a product line rather than a single product. Yet due to multiple intertwined products with different features and production deadlines, developing software for a product line is extremely complex. These challenges can hinder your company’s ability to capture the window of opportunity, maximize quality, and expand the scope of your product-line portfolio, making it difficult to obtain a competitive edge.
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Martin Bakal
, et al.
July 15, 2008
Pen-Enabled Mac Modbook? What’s Not To Like?
Most of us know about the legendary intuitive user interface of Apple Mac computers. Now Axiotron, Inc. has taken this one step further with the one and only pen-enabled tablet Mac, the Modbook, which allows users to draw and write directly on the 13.3-in. diagonal LCD screen. Having tried it for a couple of weeks, this writer found the unit’s condensed form factor and integrated pen-based user experience a real joy in terms of flexibility and control. And it’s fast!
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Roger Allan
July 14, 2008
Cadence Shoots For The Silicon Compiler Dream
It’s a long-held dream in the EDA industry: Into one end of the magic tool goes a high-level design representation of some kind, be it a functional specification a “golden” reference, or a collection of largely untimed models. Out of the other side comes a fully realized representation of the design at some lower level of abstraction, be it RTL or gate level, which achieves QoR at least equal to that achievable with hand coding in some fraction of the time.
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ED News Staff
July 14, 2008
Digi-Key Part Data Enters OrCAD Environment
Users of Cadence’s OrCAD Capture Component Information System (CIS) now have access to the wealth of engineering data offered in the Digi-Key part database. EMA Design Automation, a Cadence partner and reseller, integrated the Digi-Key database into OrCAD Capture CIS by creating the EMA Component Information Portal (CIP). CIP is a web-based solution that can be deployed enterprise-wide, providing access to the Component Information System (CIS) behind OrCAD Capture CIS.
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ED News Staff
July 14, 2008
Modeling/Simulation Tool Gets Physical
Released in a pilot version, Maplesoft’s MapleSim is a high-performance multi-domain modeling and simulation tool that’s expected to reduce the time taken to bring products to market by using physical modeling techniques.
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ED News Staff
July 1, 2008
A Mid-Year Check On The Optimism Meter
Six months ago, I predicted that emulation would be a bright spot within the EDA industry in 2008. Who could have guessed back then that our little world would be upended with the announcement of an astonishing attempt to merge two industry giants, both of whom have emulation products?
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Lauro Rizzatti
July 1, 2008
Cadence’s Grab For Mentor In Flux
Everyone expects continuing consolidation in the EDA industry, but no one expected it on the scale aspired to by Cadence Design Systems when it publicized its unsolicited attempt to acquire Mentor Graphics Corp. As has been widely reported, Mentor’s board of directors has rebuffed the $16/share offer first made in April, saying that even if it weren’t too low for their liking, it would probably run into resistance from federal anti-trust regulators.
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Staff
July 1, 2008
“Turbo” Technology Enhances RF Verification
In an effort to address the challenges of verifying wireless ICs implemented in advanced CMOS processes, Cadence has added the "turbo" technology it recently brought to the Virtuoso Spectre Circuit Simulator to its RF analysis capabilities. The claimed result is performance improvements of two- to five-times, and sometimes more, for analysis and verification of large RF circuits targeting advanced CMOS process nodes, and with no degradation in accuracy.
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Staff
July 1, 2008
Partnership Yields Concurrent Mechanical and PCB Design
In a partnership with Dassault Systèmes, Zuken has launched Board Interchanger, an integrative add-on tool for true concurrent mechanical and printed-circuit board (PCB) design. With it, MCAD engineers gain interactive access to Zuken’s board design-data interface within Dassault Systèmes’ CATIA V5 tools for virtual design by linking to CR-5000 Board Designer, providing seamless integration with other workbenches.
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Staff
July 1, 2008
Testbench Tool Exploits Distributed Compute Environments
Through an enhancement to inFact, Mentor Graphics’ intelligent testbench automation tool, large simulations can be automatically distributed across up to 1000 CPUs, extending non-redundant sequence generation to entire simulation server farms.
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Staff
June 16, 2008
RF Design Environment Gains Improved User Interface
Version 2008 of AWR’s Microwave Office design environment includes more than 100 enhancements and sweeping changes to the user interface that dramatically increase its flexibility for the user. Features such as project, elements, layout tabs, and the status window are now fully dockable and floatable, providing a design environment that is fully configurable to suit personal preferences.
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ED News Staff
June 16, 2008
Algorithmic Synthesis Is Extended To FPGAs
Building on the strength of its PICO Extreme algorithmic synthesis tool for SoCs, Synfora’s PICO Extreme FPGA extends algorithmic synthesis technology to FPGA devices. PICO Extreme FPGA enables the implementation of dramatically larger and more complex FPGA subsystems such as video codecs, wireless modems, or imaging pipelines and ensures more efficient implementation of complex algorithms than any other synthesis capability, according to Synfora.
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ED News Staff
June 16, 2008
I/O Fabric Generator Spins Complex SoC Designs
The Spinner I/O fabric generation tool for automated, bug-free I/O fabric synthesis of complex SoCs is said to automatically generate and validate the RTL for the complete I/O layer of an IC from a single-source specification.
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ED News Staff
June 16, 2008
Flow-Optimization Suite Spurs Technology Donation
The Magillem flow-optimization suite is comprised of an IP-XACT packager, platform assembly tool, complete development environment, flow control tool, and a register view kit.
The Magillem suite enables homogeneous design flow integration for various targets such as ASICs, FPGAs, electronic boards, analog/mixed-signal systems, and other complex systems. Adaptation kits have been developed for each target.
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ED News Staff
June 5, 2008
IEF 2008 Session 3: Infrastructure Changes
This session included two presentations: India—The Global Hub for Semiconductors & Electronics, by Jani Janakiraman, chairman, India Semiconductor Industry Association, and Automotive Electronics & New Technology Trends in Indian Automotive Industry, by VG (Vasuedo) Gujrathi, senior general manager, Electricals & Electronics, TATA Motors.
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Joseph Desposito
June 2, 2008
Floorplanner And Prototyping Platform Takes Lead From Specification
Called the first tool of its kind on the market, Javelin Design Automation has launched its j360 tool suite, a specification-driven virtual-silicon prototyping platform and floorplanner. Javelin’s j360 is said to realistically predict and optimize designs for implementation feasibility and quality-of-results (QoR) in parallel to their design development at the electronic system-level (ESL), register transfer-level (RTL) and netlist stages of design.
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David Maliniak
June 2, 2008
ASIC Prototyping System Speeds Time To Results
The HAPS-51T, a new addition to the HAPS (high-performance ASIC prototyping system) product family, leverages Xilinx's Virtex-5 LX330T devices to embody a suitable prototyping system for applications using high-speed serial interfaces like PCI Express, SATA, and Gigabit Ethernet. The HAPS-51T utilizes the LX330T device's 24 RocketIO GTP transceivers, adding on-board DDR2 memory and the new HapsTrak high-speed daughterboard connectivity scheme in a compact form factor.
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David Maliniak
June 2, 2008
Tool Closes Verification Loop Between ESL And Implementation
Verifying and validating the behavior of a hardware component requires appropriate sequences of stimuli (test cases) and comparison of the results provided by the device under test with the reference results. This verification is often done at the register-transfer level (RTL) and requires up to 70% of the implementation time.
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David Maliniak
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