1381 results found for Electronic Design Automation, displaying items 1 - 20
July 1, 2008
[Web Exclusive] A Mid-Year Check On The Optimism Meter
Six months ago, I predicted that emulation would be a bright spot within the EDA industry in 2008. Who could have guessed back then that our little world would be upended with the announcement of an astonishing attempt to merge two industry giants, both of whom have emulation products?
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Lauro Rizzatti
July 1, 2008
[Web Exclusive] Cadence’s Grab For Mentor In Flux
Everyone expects continuing consolidation in the EDA industry, but no one expected it on the scale aspired to by Cadence Design Systems when it publicized its unsolicited attempt to acquire Mentor Graphics Corp. As has been widely reported, Mentor’s board of directors has rebuffed the $16/share offer first made in April, saying that even if it weren’t too low for their liking, it would probably run into resistance from federal anti-trust regulators.
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Staff
July 1, 2008
[Web Exclusive] “Turbo” Technology Enhances RF Verification
In an effort to address the challenges of verifying wireless ICs implemented in advanced CMOS processes, Cadence has added the "turbo" technology it recently brought to the Virtuoso Spectre Circuit Simulator to its RF analysis capabilities. The claimed result is performance improvements of two- to five-times, and sometimes more, for analysis and verification of large RF circuits targeting advanced CMOS process nodes, and with no degradation in accuracy.
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Staff
July 1, 2008
[Web Exclusive] Partnership Yields Concurrent Mechanical and PCB Design
In a partnership with Dassault Systèmes, Zuken has launched Board Interchanger, an integrative add-on tool for true concurrent mechanical and printed-circuit board (PCB) design. With it, MCAD engineers gain interactive access to Zuken’s board design-data interface within Dassault Systèmes’ CATIA V5 tools for virtual design by linking to CR-5000 Board Designer, providing seamless integration with other workbenches.
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Staff
July 1, 2008
[Web Exclusive] Testbench Tool Exploits Distributed Compute Environments
Through an enhancement to inFact, Mentor Graphics’ intelligent testbench automation tool, large simulations can be automatically distributed across up to 1000 CPUs, extending non-redundant sequence generation to entire simulation server farms.
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Staff
June 24, 2008
[TechView: EDA] Formal Verification Suite Takes In Wider View Of Designs
If there’s ever been a knock on formal verification, it’s the amount of time it takes to do a formal run on a full design. Formal tools can only take in so much design data at a given time, forcing design teams to partition the design for formal analysis. Sure, it’ll find bugs that can’t be found any other way, but it can take quite a while to accomplish. In the latest revision of its flagship tool, JasperGold, Jasper Design Automation has made...
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David Maliniak
June 20, 2008
[Technology In The News] Layout-Dependent Modeling Boosts CMOS Gate Density
A layout-dependent circuit-design model from Toshiba helps boost gate density and improve cost-performance in next-generation 45-nm CMOS technology. More specifically, 45-nm CMOS gate density can be 2.6-times higher than that of 65-nm CMOS technology. The modeling technique was announced at this week's VLSI Symposium.
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ED News Staff
June 16, 2008
[Design Automation Conference] A 45th DAC Post-Mortem
Last week’s 45th Design Automation Conference (DAC) in Anaheim was my twelfth consecutive DAC, and it was surely the most interesting and different I’ve experienced in journalistic terms. Yeah, that was me traipsing around the show floor with my colleague Damian Mendez in tow, toting a great big video camera. It was my first experience in documenting DAC in video, and I would term it a success.
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David Maliniak
June 16, 2008
[Web Exclusive] RF Design Environment Gains Improved User Interface
Version 2008 of AWR’s Microwave Office design environment includes more than 100 enhancements and sweeping changes to the user interface that dramatically increase its flexibility for the user. Features such as project, elements, layout tabs, and the status window are now fully dockable and floatable, providing a design environment that is fully configurable to suit personal preferences.
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ED News Staff
June 16, 2008
[Web Exclusive] I/O Fabric Generator Spins Complex SoC Designs
The Spinner I/O fabric generation tool for automated, bug-free I/O fabric synthesis of complex SoCs is said to automatically generate and validate the RTL for the complete I/O layer of an IC from a single-source specification.
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ED News Staff
June 16, 2008
[Web Exclusive] Flow-Optimization Suite Spurs Technology Donation
The Magillem flow-optimization suite is comprised of an IP-XACT packager, platform assembly tool, complete development environment, flow control tool, and a register view kit.
The Magillem suite enables homogeneous design flow integration for various targets such as ASICs, FPGAs, electronic boards, analog/mixed-signal systems, and other complex systems. Adaptation kits have been developed for each target.
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ED News Staff
June 16, 2008
[ED Bookstore] Inside Steve’s Brain
Each chapter of “Inside Steve’s Brain” explores a different facet of what’s made Jobs and Apple (not to mention Pixar) so successful: organizational genius, perfectionism, elitism, despotism, passion, inventiveness. It also looks at some of the traits that have made him a legend in Silicon Valley.
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David Maliniak
June 16, 2008
[Web Exclusive] Algorithmic Synthesis Is Extended To FPGAs
Building on the strength of its PICO Extreme algorithmic synthesis tool for SoCs, Synfora’s PICO Extreme FPGA extends algorithmic synthesis technology to FPGA devices. PICO Extreme FPGA enables the implementation of dramatically larger and more complex FPGA subsystems such as video codecs, wireless modems, or imaging pipelines and ensures more efficient implementation of complex algorithms than any other synthesis capability, according to Synfora.
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ED News Staff
June 13, 2008
[Design Automation Conference] Collaboration Provides Sub 65-nm Variation-Aware IC Design Flows
This week at the Design Automation Conference (DAC), Extreme DA and semiconductor foundry UMC announced their collaboration on variation-aware IC design flows for 65-nm and finer process technologies. Extreme DA specializes in IC performance and yield-improvement software. The jointly-developed design flows reduce uncertainty and predict performance and yield by analyzing timing behavior in the presence of process variations.
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Lisa Maliniak
June 2, 2008
[ED Bookstore] Step-By-Step Functional Verification With SystemVerilog And OVM
The industry’s first book covering the Open Verification Methodology (OVM), titled “Step-by-Step Functional Verification with SystemVerilog and OVM,” provides a complete reference to adopting the OVM for functional verification. Written by Dr. Sasan Iman, a principal with SiMantis Inc., the book is being promoted by Cadence and Mentor on the OVM World Web site (www.ovmworld.org) to help the OVM community better understand and use the popular methodology.
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David Maliniak
June 2, 2008
[Web Exclusive] Floorplanner And Prototyping Platform Takes Lead From Specification
Called the first tool of its kind on the market, Javelin Design Automation has launched its j360 tool suite, a specification-driven virtual-silicon prototyping platform and floorplanner. Javelin’s j360 is said to realistically predict and optimize designs for implementation feasibility and quality-of-results (QoR) in parallel to their design development at the electronic system-level (ESL), register transfer-level (RTL) and netlist stages of design.
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David Maliniak
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